Abstract
Qubit control electronics composed of CMOS circuits are of critical interest for next-generation quantum computing systems. A CMOS-based application-specific integrated circuit (ASIC) fabricated in 14-nm fin field-effect transistor (FinFET) technology was used to generate and sequence qubit control wave forms and demonstrate a two-qubit cross-resonance gate between fixed-frequency transmons. The controller was thermally anchored to the K stage of a dilution refrigerator and the measured power was 23 mW per qubit under active control. The chip generated single-side banded output frequencies between 4.5 and 5.5 GHz, with a maximum power output of dBm. Randomized-benchmarking (RB) experiments revealed an average number of 1.71 instructions per Clifford (IPC) for single-qubit gates and 17.51 IPC for two-qubit gates. A single-qubit error per gate of and a two-qubit error per gate of were shown. A drive-induced rotation was observed by way of a rotary-echo experiment; this observation is consistent with the expected qubit behavior given the measured excess local-oscillator (LO) leakage from the CMOS chip. The effect of spurious drive-induced errors was numerically evaluated with a two-qubit model Hamiltonian and shown to be in good agreement with the measured RB data. The modeling results suggest that the error varies linearly with the pulse amplitude.
- Received 20 August 2023
- Accepted 19 January 2024
DOI:https://doi.org/10.1103/PRXQuantum.5.010326
Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.
Published by the American Physical Society
Physics Subject Headings (PhySH)
Popular Summary
The size and quality of transmon-based quantum processors are rapidly progressing. The number of qubits per quantum processor is growing year after year, and the average error rate across a quantum processor is inching closer to levels required for performing fault-tolerant quantum error correction. At a systems level, cryogenic CMOS electronics are considered a key enabling technology for realizing a fault-tolerant quantum computer; however, there are many unexplored challenges associated with integrating this technology. All of these challenges must be explored and understood to identify an optimal cryogenic control architecture. One that does not overheat the fridge and degrade the qubit performance.
The results in this work outline an experiment in which CMOS electronics were thermalized at 4 K and used to produce sequences of rf pulses for calibrating and controlling transmon qubits. The CMOS circuits were comprised of a low-power digital-to-analog converter, controlled by an on-chip digital processor, and the quantum chip was comprised of two transmon qubits capacitively coupled by a fixed-frequency resonator to produce cross-resonance entangling gates. The results highlight previously unexplored challenges associated with using a low-power ASIC to perform meaningful quantum information experiments, for example, the overhead with programming a limited-memory processor for benchmarking qubit performance and distinguishing between errors arising from device physics and errors arising from control electronics noise. This work is the first demonstration of two-qubit randomized benchmarking using cryogenic CMOS electronics and provides important insights into realizing a cryogenic control architecture for a quantum computing system.
